Processing improvements have allowed for much more logic, memory, and other functions to be integrated together on a single silicon die. Such very-large-scale-integration (VLSI) chips may have millions of transistors on a single die. Many arrays of memories can be integrated together with areas of logic.
Testing such large integrated circuits (ICs) can be difficult. The memory array may be deeply embedded within the surrounding logic, with no direct path from the embedded memory to the chip's I/O pins. The surrounding logic may be sequential, requiring long sequences of inputs to write and read memory locations. When defects occur, it may be difficult to isolate them. Some defects may not be readily visible to an external tester. Special testing logic may be added to allow direct access of the embedded memory by an external tester.
Large semiconductor memories often include redundancy to improve manufacturing yields. When a defect is found in a memory location, a redundant memory location is used rather than the defective location. Typically an entire row or an entire column is replaced when a defect is found. Decoding and muxing logic around the memory cells can be programmed to route data to the redundant row or column to avoid the faulty memory location.
FIG. 1 shows an embedded memory with built-in self-test (BIST). Chip 30 has embedded memory array 10 that is surrounded by logic (not shown) on chip 30. Row and column decoders around embedded memory array 10 allow for random access of memory locations in response to an address. BIST 20 generates addresses to embedded memory array 10 and also has pattern generator 18 that generates data to write to embedded memory array 10. The generated data and addresses from BIST 20 are written into embedded memory array 10 during a first pass in a test mode. BIST 20 can also re-generate the addresses and read back the data from embedded memory array 10 in a second pass of the test mode, using comparator 16 to compare the data read back from embedded memory array 10 to data re-generated by pattern generator 18 in the second pass.
When comparator 16 detects a data mis-match, an faulty memory location is detected. The address of the faulty memory location can be sent off-chip from BIST 20 to external tester 22 as test results 24. External tester 22 can then analyze all faulty memory locations in test results 24 to determine if repair is possible. A list of fuses to program can be generated by external tester 22 as fuse list 26, which can be sent to a fuse programmer to program fuses on chip 30. The programmed fuses cause redundant rows 14 and/or redundant columns 12 to be used rather than rows or columns with defective memory locations.
A variety of fuse technologies may be used. For example, fuses may be small conducting links that are heated by a high current to break the links, or may be links that are targeted by a laser to open the links. Fuses may also be electrically-programmable read-only memory, EPROM, or electrically-erasable programmable read-only memory, EEPROM, or other flash transistors acting as e-fuses. In some embodiments, chip 30 may be constructed from an EEPROM process, so such EEPROM transistors are readily available. Repair information from external tester 22 can be stored in a non-volatile EEPROM memory as fuses 28, rather than use blowable fuses as fuses 28 that control use of redundant rows 14 and/or redundant columns 12.
However, EEPROM transistors require special semiconductor manufacturing processes. Many chips do not need EEPROM transistors, so adding EEPROM transistors for storing fuse or redundancy information adds processing expense. Fuses may also require additional processing steps and thus increase processing costs. High-current programming logic can add to the area and cost of chip 30, while external laser-programmer machines are expensive to use and may require large-area fuses as targets, increasing die costs.
Many memory defects may be present for larger embedded memory arrays. The test results and repair map may be somewhat large, requiring a repair-map memory size of more than just a few bytes. This can increase manufacturing and fuse-programming costs. The repair information may be compressed somewhat, but complex decoding and repair logic may be needed for decoding the compressed information. Compressing the repair information may reduce repair effectiveness.
What is desired is a repairable embedded memory with redundant elements that does not require fuses, e-fuses, or non-volatile transistors to control the use of the redundant elements. An embedded memory that is repairable with only non-volatile on-chip repair memory is desirable.